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verilog-probe
EN
debugger
fpga
hdl
probe
python3
uart
verilog
Maintainers
Repository
ben-marshall/verilog-probe
Versions
2
Builds
73
Version master
/
Builds
/
#5928106
Started
Duration
Branch
master
(
1e5e4e93809d64eac31695b3ba75e8a4b43467df
)
Output
Raw log
Debug
Wrap output
View docs
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