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verilog-probe
EN
debugger
fpga
hdl
probe
python3
uart
verilog
Maintainers
Repository
ben-marshall/verilog-probe
Versions
2
Builds
73
Version master
/
Builds
/
#5928325
Started
Duration
Branch
master
(
08a470eb7f950645764ded74bfe1a34e785edf90
)
Output
Raw log
Debug
Wrap output
View docs
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